1. Field of the Invention
This invention relates to a method of passivating silicon bonds in semiconductor devices by a species, particularly deuterium.
2. Brief Description of the Prior Art
It is known that channel hot carrier (CHC) effects progressively degrade the performance of transistors, this effect being particularly apparent in VLSI CMOS transistors. Specifically, for any given bias condition, the channel current decreases over time. This aging process is thought to occur, in part, as a result of hot electrons stimulating the desorption of hydrogen from the Si/SiO.sub.2 interface region. Hydrogen is introduced by necessity during several device processing steps, for example during the sintering of wafers at an elevated temperature in a hydrogen ambient.
To avoid the problems resulting from hot carrier effects, the drain voltage and gate length of the transistors must not be changed beyond certain values. This limits the performance of the transistor. By reducing the degradation from hot carrier effects, the design limits of the transistor are improved and a higher performance, more reliable transistor is achieved. While this process improves device function, it sets the stage for subsequent hot electron degradation.
In an article entitled "Reduction of hot electron degradation in metal oxide semiconductor transistors by deuterium processing" by J. W. Lyding et al., Applied Physics Letters, Vol. 68, No. 18, Apr. 29, 1996, it is noted that replacing hydrogen with deuterium during the final wafer sintering process reduces hot electron degradation effects in metal oxide semiconductor transistors. The exact cause of this large isotope effect was not known. This substitution increased the CHC lifetime of the transistor by factors of 10 to 50, this being borne out by the applicants herein. However, Lyding et al. delivered the deuterium to the region of the gate oxide in an oven through thermal diffusion. This causes most of the deuterium to be wasted. In addition, during the sintering process, the deuterium may experience difficulty diffusing through some materials to reach the Si/SiO.sub.2 interface, especially in those cases where several layers of metalization are located between the deuterium implant and the Si/SiO.sub.2 interface.
It is also known in the case of flash memories which include a pair of insulator layers (interpolysilicon oxide layer and tunnel oxide layer) interleaved with a pair of polysilicon layers or the like, that each time the flash memory is written into or erased, charge moves through the dielectric layers surrounding the hanging polysilicon layer. This charge movement, over time, leads to a degradation of the electrical properties of the dielectric. This degradation can lead to charge loss on the storage cell, which can cause data loss. It is highly desirable to improve the quality of these surrounding dielectric layers to prevent or at least minimize this problem.
There has been no known solution to completely eliminate the wearout of the dielectric in flash memories. Generally, attention has been focused on improving the quality of the oxide or on optimizing the operation.